Classification of Passive and Solid State Devices for Assembly Processes

Standard [CURRENT]

IPC EIA/JEDEC J-STD-075B:2026-02-01

Classification of Passive and Solid State Devices for Assembly Processes

Publication date
2026-02-01
Original language
English
Pages
39

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Publication date
2026-02-01
Original language
English
Pages
39
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Short description

EIA/IPC/JEDEC J-STD-075 picks up where J-STD-020 left off by providing test methods to classify worst-case thermal process limitations for electronic components. Classification is referenced to common industry wave and reflow solder profiles including lead-free processing. The classifications represent maximum process sensitivity levels and do not establish rework conditions or recommended processes for an assembler. It outlines a process to classify and label non-semiconductor electronic component’s Process Sensitivity Level (PSL) and Moisture Sensitivity Level (MSL) consistent with the semiconductor industry’s classification levels (J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Devices and J-STD-033, Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices). Developed by ECIA, IPC and JEDEC.
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